ARM® is a supplier of microprocessor technology, offering a range of microprocessor cores for a variety of application markets and architectures that allow a licensee to create a customized microprocessor. ARM® made an architectural choice in defining their scalar floating-point architecture. Rather than storing a single scalar value in each floating-point (FP) register (regardless of the size of the value), ARM® specified that each wide FP register hold the contents of several smaller scalar FP registers. For example, in the ARM® AArch32 architecture, four 32-bit scalar FP registers are packed into a 128-bit wide register. In contrast, the ARM® AArch64 architecture specifies that each FP register hold a single scalar or vector value, regardless of the size of the data to be stored in the register.
While packing allows for a greater number of smaller scalar FP registers, the smaller FP registers are constrained to 128-bit alignment. Vector operations assume 128-bit aligned registers, while scalar operations may require 32-bit aligned registers. Therefore, when 32 or 64 bit FP registers are packed into a 128-bit wide register, one or more of the 32 or 64 bit FP registers may not be aligned as needed to perform scalar operations. Providing two different register representations (e.g., 32-bit aligned and 128-bit aligned) is needed to support both the AArch64 and AArch32 architectures. However, both of the representations are not suitable for both scalar and vector operations. Thus, there is a need for addressing this issue and/or other issues associated with the prior art.